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march 2011 doc id 17406 rev 3 1/14 AN3206 application note pcb design guidelines fo r the stm32w108 platform 1 introduction stmicroelectronics provides a ieee 802.15.4 produc t design engineer wi th a number of paths towards the successful design of a ieee 802.15.4-compliant solution based on the stmicroelectronics stm32w108 family of system-on-chip (soc) platforms. the stm32w108xx kits contain software, hardware, and documentation designed for developers to create applications efficiently on a tested and controlled platform. once the design team is familiar with st 's stm32w108xx products and the available ieee 802.15.4 software libraries and stacks, the next step in the design path involves designing application- specific hardware to meet product requirements. this application note is intended to accomp any the reference designs and provide detailed information regarding the design decisions employed within stmicroelectronics designs. in addition, it details the design guidelines for developing an application-specif ic ieee 802.15.4 design using an stm32w108xx device. after reading this document, developers should be able to successfully implement a design with an stm32w108xx device. for further information, visit the stmicroelectronics web site at www.st.com/stm32w. due to the application-specif ic nature of stmicroelectronics reference designs, st recommends that hardware designe rs familiarize themselves wit h the most recent reference design available. this document is applicable to the following stm32w108xx kits: stm32w108xx starter kit (part number: stm32w-sk) stm32w108xx extension kit (part number: stm32w-ext) stm32w108xx low-cost rf control kit (part number: stm32w-rfckit) note: the stm32w108 reference design is built on a 4-layer, fr-4 epoxy pcb. the stm32w108-based reference design includes the following elements: schematics (in pdf format) bill of materials (bom) gerber files while the reference design includes most of the information required to start an application-specific design, if additional item s needed, please contact stmicroelectronics customer support on the stmicroelectronics web site www.st.com/stm32w. www.st.com
contents AN3206 2/14 doc id 17406 rev 3 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 rf design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1.1 stm32w108 rf ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1.2 optimizing for tx (boost mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1.3 matching network circuit design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1.4 harmonic filter design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.5 band-pass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.6 antenna matching circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 rf layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2.1 pcb tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 other design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 non-rf design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 high-frequency (24-mhz) crystal reference (x1, c5, and c6) . . . . . . . . . 10 3.2 optional low-frequency crystal reference (x2, c27 and c26) . . . . . . . . . 11 3.3 1.8v regulator load capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4 1.2v regulator loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.5 1.8v net decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.6 1.8v analog to 1.8v digital filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.7 rf test connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
AN3206 reference design doc id 17406 rev 3 3/14 2 reference design figure 1 shows a block diagram of the reference design. figure 1. block diagram of stm32w108 reference design (48-pin package) the stm32w108 reference design uses an external 50/100 balun as its primary rf component. it provides an unbalanced to differential 50-to-100 ohms conversion to present the stm32w108 with its optimal load. a single inductor makes up the matching network and optimizes rf performance. a band pass filter keeps the conducted harmonics within fcc and etsi limits. due to the market demand th at ieee 802.15.4 software ma ximize their communication range, this design has been optimized accordingly. in boost mode, the stm32w108 reference design achieves a high transmit output power across the 16 channels. this section describes the design decisions behind each of the items shown in figure 1 .
reference design AN3206 4/14 doc id 17406 rev 3 2.1 rf design guidelines 2.1.1 stm32w108 rf ports the stm32w108's bi-directional rf port (pins rf_p and rf_n) provides access to a low noise amplifier (lna) and a power amplifier (pa) through a shared differential interface. the disabled high-z state of either the pa or the lna enables transmitting and receiving through the shared port without the need for a conventional t/r switch. an ?alternate? pa-only port (p ins rf_tx_alt_p and rf_tx_alt_ n) is also provided. this function is achieved via an additional pa. design considerations for this alternate pa are not covered in this document. note: the on-chip parasitic capacitance is different between the two ports and will slightly alter the off-chip matching component values. 2.1.2 optimizing for tx (boost mode) the stm32w reference design has been optimized for maximum transmitter (tx) output power in boost mode using practical components and readily available printed circuit board (pcb) substrates. the optimum load at the pa on the silicon die is approximately 700 when the pa/lna device capacitance is resonated-out. this maximizes the voltage swing at the drains of the pa devices within the available supply voltage. too large a load causes voltage limiting whereas too small a load does not make full use of the available supply voltage. figure 2 illustrates a die-level simulation of the load impedance an d its effect on pa output power. figure 2. simulated boost output power with pa load resistance optimizing the tx output performance in boost mode does not cause degradation in either normal mode or rx sensitivity. because the re ceiver is cmos-based, it amplifies the input signal voltage, rather than its current. the receiver noise is a fixed value of noise voltage that may be referred to its input. it might be expected that increasing the transformation
AN3206 reference design doc id 17406 rev 3 5/14 would yield higher signal voltage swings at the lna input, making the input referred noise less significant and thereby impr oving sensitivity. however, th is also increases the source resistance, thereby increasing the source noise voltage. in practice at the 700 level, the improvement gradient is very small and the transmit output power exhibits far greater sensitivity to load variation than receiver sensitivity. the main objective for receive sensitivity is to minimize network loss, which is a common objective when transmitting. the optimum load presented to the pins of the stm32w108 device must take into consideration not only the optimum pa load but also on-chip parasitic capacitance and package bond-wire inductance. it is estimated that the optimum load presented to the pins is 27 + j95 (series impedance). this is equivalent to a parallel resistance of 368 combined with a parallel inductance of 6.6 nh. 2.1.3 matching network circuit design the term ?matching? typically implies conjugate power matching. it is important to understand that the stm32w pa is not power matched according to the traditional definition. the term is used in this document to describe the design of an optimal pa impedance. the best way to understand st's approach towards optimizing the stm32w ?matching? is to plot on the smith chart the impedance of the ideal 700 pa load transformed by the chip/package parasitic elements. the combination of the ideal load with the parasitic elements is the conjugate of the ideal load presented to the package pins. knowing the combined load and its conjugate allows the designer to approach matching in a more traditional sense, namely, ?how do we get to 50 ?? it is also necessary at some point in the network to include a balanced-to-unbalanced (balun) conversion. use of a ?proper? balun has performance benefits related to common- mode suppression both on transmit and receive sides. there are a variety of balun architectures and solutions available. the primary objective of any of st's reference designs is to minimize design complexity and maximize time to market. therefore, st decided to implement its primary reference design with a ceramic balun. the cost of ceramic baluns is low, and they are available from a number of vendors. ceramic baluns are available in 1:1 (50 to 50 ), 2:1 (100 to 50 ), and 4:1 ratios (200 to 50 ). the magnitude of the reflection coefficient, | ? l |, in these three cases is: 1:1 (50 ) 0.8 2:1 (100 ) 0.76 4:1 (200 ) 0.8 this implies that a 2:1 ceramic balun should offer the lowest network loss, assuming identical balun loss because it requires the least transformation. investigation into ceramic balun performance from various vendors reveals that 1:1 and 2:1 ratio baluns often have an approximate 0.3 db insertion loss advantage over a 4:1 ratio. thus the use of a 2:1 ceramic balun is preferred. optimal load for stm32w (series impedance) 27 + j95 ohms
reference design AN3206 6/14 doc id 17406 rev 3 to minimize network loss, the matching topology should try to keep smith chart loci towards the center of the smith chart. to do that, the following impedance transformation options are available: series inductance followed by shunt capacitance ? this option favors lower balun ratios. ? it leads to comparatively large inductance values. ? it requires either long pcb traces or tw o discrete inductors (balanced network) which means inductor q becomes an issue. series inductance followed by shunt inductance ? similar to auto-transformer action. ? sweet-spot for 100 balun if series inductance fabricated from pcb traces since neither too long nor too short. shunt inductance followed by series capacitance ? not allowed because dc feed to pa is required from balun centre-tap. shunt inductance followed by series inductance ? favors lower balun ratios, but even at 1:1 the required series inductance is comparatively large. ? it requires either long pcb traces or tw o discrete inductors (balanced network) which means inductor q becomes an issue. pcb parasitic elements play a part in the impedance transformation and even with the tightest of layouts, traces between the matching elements will add signif icant reactance at 2.4 ghz. in particular, there will be some seri es inductance between the package pins and the first matching element. this is significant when that element is shunted because it cannot be absorbed into that reactance. since this effect cannot be avoided, it is best to take advantage of it. the option with the lowest loss and least complex arrangement is series inductance followed by shunt inductance. to make use of the pcb traces, it must be recognized that they operate more like transmission lines which travel slightly differently on the smith chart compared with real inductors and this affects the shunt inductance value. traces of 100 which equate to 150um wide on a 0.4mm thick fr-4 substrate should be used. in st's simple single-ended representation in the smith chart, the balanced pair must be modeled as a single 200 transmission line. figure 3 illustrates the impedance transformation.
AN3206 reference design doc id 17406 rev 3 7/14 figure 3. stm32w ceramic balun matching network figure 4 shows a pcb layout (layer 1). it is important that the pcb designer notice the routes between the stm32w and the balun. st recommends the use of an 0603 inductor to allow ample space for the traces to go to th e balun first with deterministic lengths. trace inductance between the inductor and balun is then absorbed into the total shunt inductance, so it may be predictably offset by reducing the physical component value. the tuned value on the reference design came out to be 3.3 nh. figure 4. layer 1 except showing the balun routes the pcb designer has the option to route the traces to the inductor first and the balun second, but this has the effect of moving the components further away from the stm32w.
reference design AN3206 8/14 doc id 17406 rev 3 by routing in this manner, pcb area and cost are wasted. it also requires the model to be updated to a three-element match, generally making it more difficult to simulate. an added benefit of using an 0603 inductor over an 0402 inductor is that better q is obtainable. the stm32w ceramic balun reference design uses a murata lqg18h series inductor which has a typical q of approximately 100 at 2.4 ghz. compare this to the commonly used lqp15m 0402 inductor, which has a typical q of approximately 50. this is worth nearly 0.2 db. the disadvantage is that it is not possible to get e24 values in 0603 style at these sorts of component values. so a small price is paid on design centering. as previously mentioned, the balun center tap is fed with a 1.8v dc feed. a decoupling capacitor is required to define the common-mode rf potential. the balun decoupling capacitor needs to be as close as possible to the balun pins and with a high quality ground connection. its value is chosen to be series re sonant with its parasitic inductance at 2.4ghz. while it would be possible to tune-out longer tracks by using a smaller capacitor value, this has the effect of making the decoupling more narrow-band, which can impact common- mode harmonic suppression. 2.1.4 harmonic filter design fcc rule 15.35 allows for a duty-cycle relaxa tion to the regulatory limits. for emberznet pro, the relaxation is 6.9 db. fcc rule 15.205 defines 'restricted bands' where harmonics must meet the levels set out in fcc rule 15.209. this is defined as -41.2 dbm/mhz up to 12.5 ghz. this applies to the 2nd, 3rd, and 5th harmonics, but not the 4th harmonic. etsi en 300 440-1 requires spurious emissions to be less than -30 dbm/mhz, 1ghz~24ghz, so this becomes the default limit for the 4th harmonic. generally, if fcc limits are met it is extrem ely unlikely that harmonics to 24 ghz would fail etsi requirements, so frequencies above the 5th harmonic are not considered here. the overall requirement is shown in ta bl e 1 . 2.1.5 band-pass filter st decided to use a band-pass filter as it is a convenient way to ensure that unwanted harmonics are filtered out and 50 ohms adaptation is guaranteed between the balun and the antenna matching circuitry. 2.1.6 antenna matching circuit a matching circuit is needed to adapt the impedance between the 50-ohm band-pass filter and the antenna. ideally a 50-ohm trace should be enough, but, in reality, antenna impedance varies with its environment. once the antenna characteristics as been measured table 1. harmonic power limits harmonic frequency limit 2nd 4810~4960 mhz ?34.3 dbm/mhz 3rd 7215~7440 mhz ?34.3 dbm/mhz 4th 9620~9920 mhz ?30.0 dbm/mhz 5th 12025~12400 mhz ?34.3 dbm/mhz
AN3206 reference design doc id 17406 rev 3 9/14 using a vector network analyzer (vna), it is easy to figure out with the help of a smith chart the value needed to compensate the de-adaptation. in our practical case, a serial capacitor (c8) and inductor (l1) have been selected. figure 5. antenna matching circuit 2.2 rf layout guidelines at 2.4ghz it does not take much for a poorly designed pcb to build up enough parasitic reactance to noticeably compromise rf performance. the following notes describe how the pcb design was implemented and some of the pitfalls that could arise in transferring the design to a product. 2.2.1 pcb tolerance volume manufacturing requires the least expensive materials to be used while meeting an acceptable level of performance. the effects of component choice have already been discussed, but the pcb also plays a major part in the matching network and so you must consider its performance. for the types of cost-sensitive applications targeted, a low-cost pcb substrate is mandatory, which means using a standard fr-4 epoxy. but wit hin the fr4 classification there are cost trade-offs to be made against: dissipation factor, df (also known as loss tangent, tan ) dielectric constant, dk (also kn own as relative permittivity, r ) generally, materials are split into 'standard loss' and 'low loss' categories, with a corresponding cost penalty. other product cons iderations such as flammability rating and lead-free assembly will narrow these choices. th ese are beyond the scope of this document. modern pcb manufacturing achieves very accurate etching and so this is not considered as a performance variable. z-axis expansion depe nds on the fr-4 material and does not alter much between vendors' material. 2.3 other design considerations please refer to section 3 for the non-rf requirements of the stm32w-based design.
non-rf design considerations AN3206 10/14 doc id 17406 rev 3 3 non-rf design considerations to operate properly, each stm32w reference design contains additional, non-rf components. these include a 24-mhz crystal, appropriate decoupling capacitors and rf test point as well as an insight port connector. 3.1 high-frequency (24-mhz) crys tal reference (x1, c5, and c6) the stm32w requires a single, accurate 24-mhz crystal source in order to develop the proper stm32w clock distributi on and ieee 802.1 5.4 timing (see figure 6 ). figure 6. 24mhz high-frequency crystal st recommends that the shunt loading capaci tors, c5 and c6, be located fairly close together and share a common ground via. the shunt capacitors and the crystal form a resonant circuit with a reasonably high q, so the circulating currents are high. as a result, despite only consuming 1ma (for example), the circulating current through the shunt capacitors may be several ma. if the grounds of the capacitors are widely separated, this several ma loop current has to flow through the ground plane to get between the two capacitors. the high current causes voltage to be developed due to the via inductance, as well as potentially inducing a voltage in the ground plane. bringing the capacitors closer together means the majority of the loop current flows in surface tracks-only and an imbalance current flows to ground, which should be small if the signal across the crystal is symmetric and sinusoidal. it is difficult to say if this really makes a difference or not, and capacitors are commonly taken to ground separately. however, the crystal is very near the rf and the vco in particular, and 24 mhz tones of the vco are very detrimental, so the problem is best avoided. due to the timing requirement s of the ieee 802.15.4-2003 st andard, this 24-mhz crystal must meet an accuracy of 40 ppm over tolerance, temperature, and aging. in addition, the crystal must have a maximum esr of 60 to control the integrated oscillator signal strengths. a manufacturing token within the stm32w device stores the crystal bias register setting. this setting is automatically determined during pcb manufa cturing testing when st's nodetest or mfg library software is used, and it is dependent upon the selected crystal. for more information on this to ken, refer to application note an3188: preparing custom devices for the stm32w108 platform . loading capacitors c5 and c6 should be chosen according to the crystal manufacturer's requirements.
AN3206 non-rf design considerations doc id 17406 rev 3 11/14 3.2 optional low-frequency crystal reference (x2, c27 and c26) the stm32w contains an integrated sleep timer that allows for software configuration of sleep/wake cycles of the wireless node. there are two options for driving the sleep timer: a 32.768 khz crystal oscillator or an internal rc oscillator. the crystal oscillator is more accurate but consumes more current than the rc oscillator. the rc oscillator is sufficient for operating st's ieee 802.15.4 software libraries and stacks. therefore, the application's sleep timing accuracy will decide if a 32-khz crystal is required. figure 7 illustrates the crystal oscillator with its load ing capacitors. to r educe the effects of overdriving the oscillator circuit within t he stm32w, st recommends an asymmetrical loading of the crystal. figure 7. 32-khz low-frequency crystal if the application does not need the 32-khz crystal, then the pins osc32a (gpio22) and osc32b (gpio23) can be used as a general-purpose io. table 2. high frequency crystal requirements parameter test conditions min. typ. max. unit frequency 24 mhz duty cycle 40 60 % phase noise from 1khz to 100khz - 120 dbc/hz accuracy initial, temperature, and aging - 40 + 40 ppm crystal esr load capacitance of 10pf 100 crystal esr load capacitance of 18pf 60 start-up time to stable clock (max. bias) 1ms start-up time to stable clock (optimum bias) 2ms
non-rf design considerations AN3206 12/14 doc id 17406 rev 3 3.3 1.8v regulator load capacitor the stm32w operates over a supply voltage (v brd ) of 2.1 to 3.6v. an integrated 1.8v regulator converts v brd down to a trimmed 1.8v. to st abilize the integrated regulator, a 2.2 f ceramic loading capacitor is required on the output of vreg_out of the stm32w. a series resistor (r5) is used to keep the minimum esr of the loading capacitor below 1 ohm. this is shown in figure 8 . figure 8. 1.8v regulator loading capacitance 3.4 1.2v regulator loading the stm32w contains an integrated 1.2v regulator to drive the core logic. by driving the core at this lower v dd potential, reduced cu rrent consumption is achieved. to utilize this regulated voltage, a pcb designer should connect pin vdd_core_0 to pin vdd_core_1. if you would like to drive the core at 1.8v, then the 1.8v net should be connected to both pins vdd_core_0 and vdd_core_1. a 1f ceramic loading capacitor should be placed close to pin vdd_core_0. in addition, a 10nf decoupling capacitor should be place close to pin vdd_core_1. 3.5 1.8v net decoupling to minimize noise and coupling paths into the stm32w, decoupling capacitors must be placed on each of the vdd pins. all decoupling capacitors should be placed as close to the stm32w as possible as well as in between the source point (via) and the stm32w pin. in addition, all values should be maintained as defined by the stm32w reference design. 3.6 1.8v analog to 1.8v digital filtering to keep the radio active current at 36 ma, st recommends adding a single element filter (resistor) between the digital and analog 1.8v nets, 1.8v_a and 1.8v_d, respectively (see figure 9 ). this resistor maintains a reduced bias current for the digital logic within the stm32w. if this resistor is not used, th e rx current will increase by 1ma to 37ma.
AN3206 revision history doc id 17406 rev 3 13/14 figure 9. digital vdd filter the lower current consumption also allows for a reduction in the digital 1.8v domain noise. this means the rx sensitivity improves by 2db when using the 10-ohm resistor. 3.7 rf test connector to assist with manufacturing testing of the printed circuit assemblies, st recommends having the possibility to solder an uf.l ty pe rf connector such as those from hirose. after reading this document if you have questions or require assistance with the procedures described in this document, please contact stmicroelectronics support at http://www.st.com/stm32w. 4 revision history table 3. document revision history date revision changes 29-apr-2010 1 initial release. 08-dec-2010 2 updated section 3.4: 1.2v regulator loading on page 12 . 16-mar-2011 3 added support for stm32w108xx kits; updated ?zigbee? and ?emberznet? references with ?ieee 802.15.4?; and updated stm32w website url.
AN3206 14/14 doc id 17406 rev 3 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2011 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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